Technical data

Troubleshooting
Dealing with HPMC (Uncorrectable Error)
4-22
HPMC Caused by a Data Cache Parity Error
For example, an HPMC interruption is forced when a data cache parity error is detected
during a load instruction to the memory address space or during a data cache flush opera-
tion.
Table 4-5 shows an example of the HPMC error information retrieved from Stable Storage
by the PIM command from the Interactive Testing Debug Environment.
The value in the CPU State word indicates that register values and addresses stored in Sta-
ble Storage at the time of the HPMC were saved.
The value of the Cache Check word identifies that logic in the processor module detected
a (data) cache parity error. Ignore the value in the System Controller Status word.
Table 4-5 Processor Module Error (Data Cache Parity)
Word Value
Check Type 0x80000000
CPU State 0x9e000004
Cache Check 0x40000000
TLB Check 0x00000000
Bus Check 0x00000000
Assists Check 0x00000000
Assists State 0x00000000
System Responder Address 0x00000000
System Requester Address 0x00000000
System Controller Status 0x00000nnn