Specifications

9
Instruction replay technology
The processor core pipeline management efficiency is improved by means of new error recovery path techniques. Dual
domain multi-threading provides for two paths for flushing the pipeline and five paths for retrying the pipeline.
Integrated memory controllers and Scalable Memory Interconnect
The Scalable Memory Interconnect (SMI) connects to the Intel Scalable Memory Buffers to support larger physical
memory configurations and dramatically improves communication channels between the processor cores and main
memory. Each processor has two integrated memory controllers that provide peak memory bandwidth up to 34 GB/s
read, plus up to 11.2 GB/s concurrent write. The memory subsystem is capable of supporting 32 GB DIMMs, hence
duplicating the supported memory from prior generation.
Enhanced instructions-level parallelism
Instructions-level parallelism (ILP) refers to the ability to process multiple instructions on each software thread.
Each core within the Itanium processor 9500 series disperses instructions to a 12 wide, 11 stage deep execution
pipeline. The per core resources consist of:
• Six integer units
• One integer multiply unit
• Four multimedia units
• Two load-store units
• Three branch units
• Two floating point units supporting extended, double, and single precision computations
• No Operation (NOP) squashing
• 96 entry instruction buffer duplicated for dual-domain multithreading
• 160 additional stacked general registers (32 additional registers over the 9300 series processor)
Other processor features are dynamic prefetch, branch prediction, register scoreboard, and non-blocking cache. To
support dual domain multithreading, each core duplicates its architectural state registers, thus enabling greater
performance.