Specifications

Processor technologies

Intel Itanium processor 9500 series micro-architecture features a record 3.1 billion transistors. The most significant

improvements in the Itanium processor 9500 series include doubling the number of processing cores to eight from the

previous Itanium processor 9300 series, increased maximum core frequency of 2.53 GHz from 1.86 GHz, 50 percent

frequency increase in IO and memory interfaces, greater physical memory capacity and next-generation reliability,

availability, serviceability (RAS) and manageability features.

A new core micro-architecture is implemented. It improves power efficiency and significantly improves frequency. The

core features an 11 stage in-order, decoupled front end and back end pipeline. It employs replay and flush mechanisms

versus the previous global stall micro-architecture. A hardware data prefetcher, data access hints and TLB concurrent

accesses improvements, are among other new core features implemented in the Itanium processor 9500 series to

improve overall performance. The HP Integrity server blades are equipped with Itanium processor 9500 series. Each

processor can host up to eight processing cores. Each processor features two memory controllers and QPI technology to

boost bandwidth between processors, memory, and I/O subsystems.

Multilevel caches

Intel Itanium processor 9500 series have a three-level cache hierarchy (figure 4)

• An on-core 32 KB Level 1 (L1) cache split into 16 KB for instruction and 16 KB for data. The L1 cache can deliver six

instructions every clock cycle.

• The on-core Level 2 (L2) cache is organized as 512 KB instruction and 256 KB data caches.

• Each processor core features up to 4 MB Level 3 (L3) cache. All L3 caches amount to a total of up to 32 MB per

processor socket.

• Each memory controller also features a 1.5 MB directory cache.

Hyper-threading

With eight multi-threaded cores, each processor can execute up to sixteen simultaneous software threads. Thread

management has improved compared to previous Itanium generations. The processor adds more features over prior

generations improving performance and throughput. As in previous generations, the core duplicates all the architectural

and some micro-architectural state to create two logical processors in each physical core.

The Itanium processor 9500 series introduces the concept of two thread domains within the pipeline where the

instruction fetch (Front End) and execution (Back End) operate independently. This concept is referred to as dual domain

multi-threading. With independent thread domains and a fully duplicated instruction buffer, the Front End can perform

instruction fetch for either thread regardless of which thread the Back End is executing. This feature improves

application response time and overall system throughput.