Specifications

10
QuickPath Interconnect architecture
Each QPI consists of two unidirectional links that operate simultaneously in opposite directions using differential signaling.
Unlike a typical serial bus, the QPIs transmit data packets in parallel across multiple lanes, and packets are broken into
multiple parallel transfers. Each link is comprised of 20 1-bit lanes. A maximum of 16 bits (2 bytes) are used to transfer data
and error correction use the remaining 4 bits. The link allows a maximum of 12.8 gigabytes per second in each direction, for
a total bandwidth of 25.6 gigabytes per second. If an application requests data from the memory of another processor, the
QPI uses high-bandwidth inter-processor communication to retrieve the data. The communication between processors
within the same blade server is twice as fast when compared to the communications through the Integrity Blade Link.
Figure 5 shows the HP Integrity BL860c i4 Server Blade QPI links implementation.
Figure 5. HP Integrity BL860c i4 Server Blade QPI links interconnectivity diagram. Notice the blade link connector to allow multiple
server blades interconnect. QPI links connected through the blade link connector are half width.
Thermal logic technologies
Itanium processor 9500 series power and thermal management is different from the 9300 series. Thermal design
power (TDP) control mechanism is via regulating the instruction dispersal, instead of frequency change; via core level
monitoring instead of socket.
The Power Management Controller (PMC) monitors the core activity levels in real time, and adjusts the activity to stay
within TDP. The controller calculates a “Digital Activity Factor” per core. Each core enforces its own “Activity Factor
Throttling” (AFT) to keep the processor at TDP. With AFT, the instruction dispersal in the particular core is lowered to
keep the core within TDP, instead of changing the processor frequency. The PMC allows full activity for applications that
operate under the activity limit.