HP-UX Floating-Point Guide

38 Chapter 2
Floating-Point Principles and the IEEE Standard for Binary Floating-Point Arithmetic
Floating-Point Formats
Figure 2-3 IEEE Quad-Precision Format
NOTE On HP 9000 systems, the most significant word is stored at a lower
memory address than the least significant word. If, for example, a
double-precision value is stored at address 0x1000, the least significant
word is stored at address 0x1004. If a quad-precision value is stored at
address 0x1000, the least significant word is at address 0x100C. This
ordering is often referred to as “big-endian.”
The Fraction Field
For normalized values (see “Normalized and Denormalized Values” on
page 41), the fraction represents a value greater than or equal to 1.0 and
less than 2.0. Each bit in the fraction represents the value 2 raised to a
negative power. For example, the first bit represents the value 2
−1
(0.5),
the second bit is 2
−2
(0.25), and so on. The sum of 1.0 and the values
represented by all these bits is the value of the fraction. The 1.0 in the
sum corresponds to the zeroth fraction bit, 2
0
. Since this bit would
always be set for a normalized value, it is not included in the actual
format, but it is implied. It is sometimes referred to as the fraction
implicit bit or the hidden bit.