HP-UX Floating-Point Guide

Glossary 227
Glossary
sign, 11 bits for the exponent, and
52 bits for the fraction. See also
single-precision, quad-
precision.
error condition See exception
condition.
exception See exception
condition.
exception condition A condition
that may require special handling
to make further execution of an
application meaningful. In many
applications, the occurrence of an
exception indicates an error. The
IEEE standard specifies five
exception conditions: the inexact
result condition, the overflow
condition, the underflow
condition, the invalid
operation condition, and the
division by zero condition. See
also trap handler.
exception flags A group of bits
in the floating-point status
register. If an exception
condition occurs and the
corresponding exception trap
enable bit is not set, the floating-
point unit (FPU) sets the
corresponding exception flag to 1,
but does not cause a trap.
exception trap enable bits A
group of bits in the floating-point
status register. If an exception
condition occurs and the
corresponding exception trap
enable bit is set, the floating-
point unit (FPU) causes a trap.
When the enable bit equals 0, the
exception usually sets the
corresponding exception flag to
1 instead of causing a trap.
exponent In a floating-point
representation, the bits that
represent a value to which 2.0 is
raised. See also fraction, sign bit.
fast underflow mode See flush-
to-zero mode.
fastmode See flush-to-zero
mode.
finite value A representable
floating-point value (that is, not an
infinity or a NaN (Not-a-
Number)).
floating-point Of or pertaining
to the method by which computer
systems represent and operate on
real numbers. The IEEE
standard specifies that a floating-
point value consists of a sign bit, a
fraction, and an exponent.