HP-UX Floating-Point Guide

Chapter 7 187

Performance Tuning

Cache Aliasing

HP 9000 systems employ high-speed cache memory to store the most

recently used instructions and data. The location of instructions and

data in the cache is a function of the n low-order bits of the address of the

data or instruction. Consequently, instructions and data that have the

same n low-order bits compete for the same cache space. Such competing

objects are called cache aliases of each other.

Programs that contain loops in which two or more cache aliases are

referenced will run more slowly than expected because the system must

repeatedly swap aliased objects into and out of the cache.

Data cache aliasing can occur when two data objects that are far apart

in virtual memory (so that their addresses have the same low-order bits

but different high-order bits) are referenced in the same loop.

Instruction cache aliasing, which is less likely to happen but has

more serious effects, can occur when two routines invoked in a loop are

aliases of each other. In this case, the invocation of the second routine

forces the ﬁrst routine out of the cache, and the next time through the

loop the ﬁrst routine pushes the second routine out of the cache.

Table 7-1 illustrates this situation using a 1K-byte cache example. If the

cache addresses of subr1 and subr2 overlap signiﬁcantly, instruction

cache aliasing can produce a severe performance degradation.