HP-UX Floating-Point Guide

Chapter 5 129
Manipulating the Floating-Point Status Register
Run-Time Mode Control: The fenv(5) Suite
Table 5-1 IEEE Exception Bits
Enables Exception trap enable bits. An enable bit is
associated with each IEEE exception. When an enable
bit equals 1, the corresponding trap is enabled. When
an enable bit equals 0, the corresponding IEEE
exception sets the corresponding flag to 1 instead of
causing a trap. The functions fegettrapenable and
fegettrapenable manipulate these bits.
RM Rounding mode for all floating-point operations. The
values corresponding to each rounding mode are shown
in Table 5-2. The functions fegetround and
fesetround manipulate these bits.
Table 5-2 Rounding Modes
D The D bit. When this bit is set to 1, flush-to-zero
underflow mode is enabled (see “Underflow Mode:
fegetflushtozero and fesetflushtozero” on page 145).
The functions fegetflushtozero and
fesetflushtozero manipulate this bit.
Bit
Name
Description
V Invalid operation
Z Division by zero
O Overflow
U Underflow
I Inexact result
Rounding
Mode
Description
0 Round to nearest
1 Round toward zero
2 Round toward +infinity
3 Round toward −infinity