HP-UX Floating-Point Guide

128 Chapter 5

Manipulating the Floating-Point Status Register

Run-Time Mode Control: The fenv(5) Suite

NOTE Be careful if you use these functions at higher optimization levels (2 and

above). Optimization may change the order of operations in a program,

so that a call to one of these functions may be placed after an operation

you want the function to affect, or before an operation whose result you

want the function to check. These functions will then produce

unexpected results. (If it is possible to isolate the part or parts of your

program that call these functions, you could place them in a separate

module and compile it at a lower optimization level than the rest of the

program. You may also use the FLOAT_TRAPS_ON pragma to suppress

optimization for part of your program. For information, see the C online

help (cc +help).

The PA-RISC Floating-Point Status Register

The PA-RISC ﬂoating-point status register is fr0L, the left half of fr0.

Figure 5-1 shows the structure and contents of fr0L. Fields marked Res

are reserved for future use.

Figure 5-1 PA-RISC Floating-Point Status Register (fr0L)

PA-RISC 2.0 Architecture and the PA-RISC 1.1 Architecture and

Instruction Set Reference Manual describe the contents of fr0L in detail.

The ﬁelds manipulated by the fenv(5) functions are as follows:

Flags Exception ﬂags. A ﬂag bit is associated with each

IEEE exception. If the corresponding enable bit is not

set, the ﬂoating-point unit sets an exception ﬂag to 1

when the corresponding exception occurs, but does not

cause a trap. Table 5-1 shows the bit names and the

corresponding exceptions. The functions

fegetexceptflag, fesetexceptflag,

feclearexcept, fetestexcept, and

feraiseexcept manipulate these ﬂags.