vps_pagesize.5 (2010 09)

v
vps_pagesize(5) vps_pagesize(5)
(Tunable Kernel Parameters)
NAME
vps_pagesize - minimum (in kilobytes) of system-selected page size
VALUES
Default
16 (KB)
Allowed values
Minimum:
4 (KB)
Maximum:
4194304 (KB)
DESCRIPTION
The Translation Look-aside Buffer (TLB) is a microprocessor feature for virtual memory, where the most
recent physical to virtual address translations are cached, in the expectation that these translations are
likely to be needed again soon. This is based on the principles of spatial and temporal locality of address
references in programs. Historically, the TLB were entirely managed within hardware to achieve speed
optimizations while sacrificing the flexibility of software implementations. For example, easily changed
algorithms or table implementations.
In recent years, the flexibility of a software implementation of the TLB has regained importance over
pure hardware speed. Specifically, the idea of logical grouping of physical frames (whose size if fixed in
hardware) into "superpages" or "large pages", that can be represented in software TLB algorithms using a
single base address translation for many physical frames, significantly reduces the lost cycles due to page
faults (assuming reasonable spatial and temporal locality). For example, consider a scientific application
working on an array where each element requires 1 KB of memory. Using the usual 4 KB physical frame
size and referencing the array sequentially causes a page fault that requires the page be read into
memory from disk or swap, and loads the TLB with the frame base address translation at every fifth ele-
ment.
If a user application does not use the
chatr command to specify a page size for the program text and
data segments, the kernel automatically selects a page size based on system configuration and object size.
This selected size is then compared to the maximum page size defined by the vps_ceiling
tunable,
and if the selected size is larger, the value of
vps_ceiling is used instead. Then, the value is com-
pared against the minimum page size as set by vsp_pagesize, and the larger of the two values is used.
Who Is Expected to Change This Tunable?
Anyone.
Restrictions on Changing
Changes to this tunable take effect for subsequent physical memory allocations. Physical memory already
in use is not affected.
When Should the Value of This Tunable Be Raised?
This tunable can be raised when processes on the system access their text and data in a regular fashion,
and over a range of data larger than the current value. For example, if this tunable is set to 16 KB, but
almost every process on the system repeatedly works with a four or five distinct 256 KB data sets, then
raising the tunable to 256 would reduce the page faulting for these processes because 16 of the previously
16 kilobyte pages are now addressed by a single 256 kilobyte translation.
Average system behavior is not likely to display uniformity of memory access and the optimal value is not
easy to determine, so this tunable only represents the lower value for the kernel heuristic and may not
change the actual system behavior.
What Are the Side Effects of Raising the Value?
Memory allocations will require larger groups of contiguous pages because the kernel heuristic was not
already choosing the larger value.
Requiring larger virtual pages may lead to undesirable system behavior. This is especially true when
many processes with small or fragmented data/code sets are active. Every virtual page referenced by the
application, regardless of actual usage within that page, requires that the entire page work of contiguous
physical frames of memory be present. For example, you cannot swap out half of a large virtual page.
Many contiguous frames may not always be possible and may cause memory stalls on allocation that are
not strictly needed. In addition, the waste of physical frames in this case would probably lead to increase
swap usage, further degrading system performance.
HP-UX 11i Version 3: September 2010 − 1 − Hewlett-Packard Company 1