ttrace.2 (2010 09)

t
ttrace(2) ttrace(2)
__ar32 R/W Reads as 0
__ar_unat
__ar36
R/W R/W
__ar_fpsr
__ar40
R/W R/W
__ar_pfs
__ar64
R/W R
__ar_lc
__ar65
R/W R/W
__ar_ec
__ar66
R/W R/W
0 == syscall context, non-zero == interrup-
tion context
__reason RR
Low-order 2-bits indicate slot number.__ip R/W R/W
Current Frame Marker corresponding to
__ip
__cfm R/W R/W
May not be set if not previously set.__ed R/W Reads as 0
__cr_isr
__cr17
R
__cr_iipa
__cr22
R
On PA-RISC systems, the words at offset addr in the
save_state structure are
returned to the calling process. The data argument is the size of the read. The addr2
argument points to the location in the calling process’s address space where the data will
be written. The addr argument must be word-aligned and addr+data must be less than
or equal to
sizeof (save_state_t)
(see the file <machine/save_state.h>).
Note: On Itanium-based systems, 8, 9 and 16 byte reads are supported. Static general
registers may be read with 8 or 9 byte requests. The NaT bit corresponding to the gen-
eral register is returned in bit 0 of the 9th byte if requested. Floating point register
reads must be 16 byte requests. All other register reads must be 8 byte requests. Indivi-
dual bits, such as __p1...__p63, will be returned in bit 0 of an 8 byte word.
On PA-RISC systems, only 4 and 8 byte reads and writes are currently supported.
TT_LWP_WUREGS
With this request, on Itanium-based systems: data bytes of data pointed to by addr2 are
written to the register specified by addr which must be a __uregs_t value as noted above.
On PA-RISC systems: data bytes of data pointed to by addr2 are written at offset addr in
the save_state structure. Only these locations can be written in this way: the gen-
eral registers, most floating-point registers, a few control registers, and certain bits of the
interruption processor status word.
Note: On Itanium-based systems, 8, 9 and 16 byte writes are supported. Static general
registers may be written as 8 or 9 byte requests. Bit 0 of the 9th byte is written to the
NaT bit corresponding to the general register if requested. An 8 byte write to a static
general register will clear the corresponding NaT bit. Floating point register writes must
be 16 byte requests. All other register writes must be 8 byte requests.
On PA-RISC systems, only 4 and 8 bytes reads and writes are currently supported.
Vectored Requests
For all vectored requests (those prefixed by
TT_VEC_), pid is the process ID of the target process.
TT_VEC_GENERIC
This request performs a series of requests on arbitrary threads within a single target
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