make.1 (2010 09)

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make(1) make(1)

NAME

make - maintain, update, and regenerate groups of programs

SYNOPSIS

make [-f makeﬁle][

-bBdeiknpPqrsStuw

][macro_name=value ][names]

DESCRIPTION

Makeﬁle Structure

A makeﬁle can contain four different kinds of lines: target lines, shell command lines, macro deﬁnitions,

and include lines.

Target Lines

Target lines consist of a blank-separated, nonnull list of targets, followed by a colon (

:) or double colon

(

::), followed by a (possibly null) list of prerequisite ﬁles called dependents. Pattern Matching Nota-

tion (see regexp (5)) is supported for the generation of ﬁle names as dependents.

Shell Command Lines

Text following a semicolon (

;) on a target line, and all following lines that begin with a tab are shell com-

mands to be executed to update the target (see the Environment subsection below about

SHELL). The

ﬁrst line that does not begin with a tab or

# begins a new target deﬁnition, macro deﬁnition, or include

line. Shell commands can be continued across lines by using a <backslash><newline> sequence.

Target lines with their associated command lines are called rules .

Macros

Lines of the form string1

= string2 are macro deﬁnitions. Macros can be deﬁned anywhere in the

makeﬁle, but are usually grouped together at the beginning. string1 is the macro name; string2 is the

macro value. string2 is deﬁned as all characters up to a comment character or an unescaped newline.

Spaces and tabs immediately to the left and right of the

= are ignored. Subsequent appearances of

$(string1 ) anywhere in the makeﬁle (except in comments) are replaced by string2 . The parentheses are

optional if a single character macro name is used and there is no substitute sequence. An optional substi-

tute sequence,

$(string1 [:subst1 =[subst2 ]]) can be speciﬁed, which causes all nonoverlapping

occurrences of subst1 at the end of substrings in the value of string1 to be replaced by subst2 . Substrings

in a macro value are delimited by blanks, tabs, newline characters, and beginnings of lines. For example,

OBJS = file1.o file2.o file3.o

then

$(OBJS:.o=.c)

evaluates to

file1.c file2.c file3.c

Macro values can contain references to other macros (see the WARNINGS section):

ONE =1

TWELVE = $(ONE)2

The value of $(TWELVE) is set to $(ONE)2 but when it is used in a target, command, or include line, it

is expanded to 12. If the value of ONE is subsequently changed by another deﬁnition further down in the

makeﬁle or on the command line, any references to $(TWELVE) reﬂect this change.

Macro deﬁnitions can also be speciﬁed on the command line and override any deﬁnitions in the makeﬁle.

(UNIX Standard only, see standards (5). Macros on the command line are added to the

MAKEFLAGS

environment variable. Macros deﬁned in the MAKEFLAGS environment variable, but without any com-

mand line macro, adds the macro to the environment overwriting any existing environment variable of

the same name.)

Certain macros are automatically deﬁned for

make (see Built-in Macros). See the Environment subsec-

tion for a discussion of the order in which macro deﬁnitions are treated.

The value assigned to a macro can be overridden by a conditional macro deﬁnition. A conditional macro

deﬁnition takes on the form target

:= string1 = string2. When the target line associated with target is

being processed, the macro value speciﬁed in the conditional macro deﬁnition is in effect. If string1 is

previously deﬁned, the new value of string1 will override the previous deﬁnition. The new value of

HP-UX 11i Version 3: September 2010 − 1 − Hewlett-Packard Company 1

Summary of content (12 pages)

PAGE 1
make(1) make(1) NAME make - maintain, update, and regenerate groups of programs SYNOPSIS make [-f makefile ] [-bBdeiknpPqrsStuw] [macro_name =value ] [names ] DESCRIPTION Makefile Structure A makefile can contain four different kinds of lines: target lines, shell command lines, macro definitions, and include lines.
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make(1) make(1) string1 takes effect when target or any dependents of target are being processed. Include Lines If the string include appears as the first seven letters of a line in a makefile, and is followed by one or more space or tab characters, the rest of the line is assumed to be a file name and is read and processed by the current invocation of make as another makefile after any macros in the file name have been expanded. The default behaviour of make is to use .
PAGE 3
make(1) make(1) The -n option specifies printing of a command line without execution. However, if the command line has the string $(MAKE) or ${MAKE} in it or + as a prefix, the line is always executed (see discussion of the MAKEFLAGS macro under Environment ). The -t (touch) option updates the modified date of a file without executing any commands. A command line is normally printed before it is executed, but if the line has a @ at the beginning, printing is suppressed.
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make(1) make(1) -r Clear suffix list and do not use the built-in rules. -s Silent mode. Command lines are not printed to standard output before their execution. This mode is also entered if the special target name .SILENT appears in the makefile. -S Terminate if an error occurs while executing the commands to bring a target up-to-date. This is the default and the opposite of -k. If both -k and -S are specified, the last one given is used.
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make(1) make(1) MAKEFLAGS and passed to the recursive invocations of $(MAKE) or ${MAKE}. This is one way of debugging all of the makefiles for a software project without actually executing any of the commands. Each of the commands in the rules is given to a shell to be executed. The shell used is the shell command interpreter (see sh(1)), or the one specified in the makefile by the SHELL macro.
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make(1) make(1) .Y.C .Y.o .Y˜.C .Y˜.Y .Y˜.o Double suffix inference rules (.c.o) define how to build x.o from x.c. Single suffix inference rules (.c) define how to build x from x.c. In effect, the first suffix is null. Single suffix rules are useful for building targets from only one source file; e.g., shell procedures and simple C programs. A tilde in the above rules refers to an SCCS file (see sccsfile (4)). Thus, the rule .c˜.o would transform an SCCS C source file into an object file (.o).
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make(1) make(1) $(LIB)(file.o) both refer to an archive library that contains file.o (this assumes the LIB macro has been previously defined). The expression $(LIB)(file1.o file2.o) is not valid. Rules pertaining to archive libraries have the form .xx .a where xx is the suffix from which the archive member is to be made. An unfortunate byproduct of the current implementation requires the xx to be different from the suffix of the archive member. Thus, one cannot have lib(file.o) depend upon file.
PAGE 8
make(1) make(1) dependents, at which point the recursion stops. Not all targets processed by make appear as explicit targets in the makefile; some of them are explicit dependents from the makefile while others are implicit dependents generated as make recursively updates the target. For instance, when the following makefile is executed: pgm: a.o b.o cc a.o b.o -o pgm the following series of targets to be made is generated: --- pgm with two dependents and an explicit rule to follow --- a.
PAGE 9
make(1) make(1) In addition to the built-in macros listed above, other commonly used macros are defined by make. These macros are used in the default inference rules, and can be displayed with the -p option. These macros can be used in target rules in the makefile. They can also be redefined in the makefile. $$@ The $$@ macro has meaning only on dependency lines. Macros of this form are called dynamic dependencies because they are evaluated at the time the dependency is actually processed.
PAGE 10
make(1) make(1) International Code Set Support Single and multi-byte character code sets are supported. RETURN VALUE make returns a 0 upon successful completion or a value greater than 0 if an error occurred. If the -q option is specified, make returns 0 if the target was up-to-date and a value greater than 0 if the target was not up-to-date. EXAMPLES The following example creates an executable file from a C source code file without a makefile, if program.
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make(1) make(1) SEE ALSO cc_bundled(1), cd(1), lex(1), mkmf(1), sh(1), environ(5), lang(5), regexp(5), standards(5). A Nutshell Handbook, Managing Projects With Make by Steve Talbot, Second Edition, O’Reilly & Associates, Inc., 1986. STANDARDS CONFORMANCE make: SVID2, SVID3, XPG2, XPG3, XPG4, POSIX.
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(Notes) A (Notes) mA 12 Hewlett-Packard Company −1− HP-UX 11i Version 3: September 2010