HP Caliper User's Guide

This problem generally only occurs when there is a loop that has a statically
mispredicted branch. This can lead to accesses to code that is never executed and
thus never in the cache, but is continually being accessed by the mispredicted
branch. This results in an ITLB miss, which is then dismissed before the trap is
actually taken.
%DTLB H/W Update
This is the percentage of level 2 ITLB misses out of ITLB hardware inserts. This is
a metric of the effectiveness of the HPW.
348 Event Set Descriptions for CPU Metrics