HP Caliper User's Guide

• BRIL
Bus Read Invalidate Line is the transaction used when a store miss occurs, thus a
read for ownership. In Itanium 2, this transaction is also used when a store hit
occurs on a shared line. In this case, the BRIL is used to invalidate all remote copies
on this cache line and have the memory controller return the line we already have
to the cache. Itanium 2 does not implement the BIL optimization, which would
have allowed remote copies to be invalidated without performing a superfluous
memory request.
• BWL
Bus Writeback Line is used when a dirty cache line is replaced as a consequence
of servicing a BRL or BRIL bus transaction.
• BRC
This is the number of current memory read transactions on the bus.
• BIL
Bus Invalidate Line is used to cause lines to be flushed from the cache. Since Itanium
2 does not implement the BIL optimization, this can only be generated by the fc
(flush cache) instruction. This is a zero-byte memory read transaction, although
an implicit writeback will occur if the BIL hits a modified line.
• Ccast Out
These zero-byte write transactions would normally only occur in systems that use
directory-based cache coherence. The purpose of this transaction is to inform the
coherency directory that a clean cache was evicted from the CPU's cache (that is,
it is no longer an owner of the cache line). Snoopy-based cache coherency systems
do not require this notification, because all caches are automatically interrogated
on all memory cache line reads/writes.
• PRTL
This is the number of partial (less than 128 byte) reads (BRP) or writes (BWP) per
second. Partial transactions are normally due to reading/writing memory-mapped
I/O control registers, semaphore operations, clean castouts (if monitoring a system
with directory-based cache coherency), and sending interprocessor interrupts.
sysbus Event Set 343