HP Caliper User's Guide

l2dcache Event Set
The l2dcache event set provides miss rate information for the L2 data cache on
dual-core Itanium 2 and Itanium 9300 quad-core processor systems. On other Itanium
2 systems, use the l2cache event set, which provides the miss rate information for
the unified L2 cache.
The L2 data cache metrics include miss information for integer loads that miss the L1
cache, memory operations not handled by the L1 cache (that is, integer stores), lfetch
instructions, and floating-point load/store operations.
There are a number of issues regarding L2 data cache access that need to be considered
when interpreting L2 data cache measurement results. The L2 cache will not count
fetches to the second half of a line if the fetch for the first part is already counted.
Secondary misses are counted as data references, and semaphore operations are counted
as a single atomic operation. Only requests that have entered the OZ queue are counted.
And these instructions are not counted: FROM_CCV, SETF, PTC_G, FWB, MF, MFA,
SYNCI, SYNCIA, PTCM, FC, and CC.
If you use this event set, the default is to make the measurements irrespective of CPU
operating state (that is, user, system, or interrupt states). By default, the idle state is
not included in the measurement. You can use command-line options to limit the scope
of the measurement. Specifically, you can:
• Limit measurement to a specific privilege level: -m
event_set[:all|user|kernel]
• Include idle: --exclude-idle False
• Exclude the interruption state: --measure-on-interrupts off
• Only measure the interruption state: --measure-on-interrupts only
The event per kinst (event per 1000 instructions) metrics are computed using all
instructions retired. This includes nops, predicated off instructions, failed speculation
and instructions and associated recovery code as well as the architecturally visible
instruction. You can eliminate idle loops effects by using the command-line option
--exclude-idle True (which is the default). The effects of failed speculative
operations and TLB misses cannot be directly eliminated, but you can get an estimate
of the impact of events from the cspec, dspec, and tlb event sets. You can use the
cpi event set to obtain the fraction of all instructions retired that have an architecturally
visible result, except for predicated off branches, which are counted as useful instructions
(non-taken branch) by the Itanium 2 PMU.
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take
into account any command-line options you might use.
l2dcache Event Set 327