HP Caliper User's Guide

• Writeback Hits Per Kinst
This is the number of cache line writebacks that hit the L3 cache per 1000 retired
instructions, including nops and predicated off instructions.
• Writeback Misses Per Kinst
This is the number of cache line writebacks that miss the L3 cache per 1000 retired
instructions, including nops and predicated off instructions. Writeback misses are
sent directly to memory; they do not allocate the line in the L3 cache.
• Writebacks Per Kinst
This is the total number of L2 cache writebacks (L3 hit and miss) per 1000 retired
instructions, including nops and predicated off instructions.
• Instr Per Access
This is the ratio of the total number of instructions retired per L2 cache access,
including nops and predicated off instructions. The L2 cache accesses include RSE
stores, VHPT loads, all integer and RSE loads that miss the L1 data cache, all integer
stores, all floating-point loads/stores, semaphores (counted once), and instruction
fetches/prefetches that miss the L1 instruction cache.
• %Miss
This is the percentage of all the L2 unified cache misses out of the total number of
L2 cache accesses. Accesses include instruction fetches/prefetches that miss the L1
instruction, all integer and RSE loads that miss the L1 data cache, all RSE and
integer stores, all floating-point loads/stores, and semaphore (counted once)
operations.
326 Event Set Descriptions for CPU Metrics