HP Caliper User's Guide

The metrics are:
• Total - Misses Per Second
This is the total number of L2 cache misses per second. It includes all instruction
prefetch misses, instruction demand misses, and data misses.
• Pfetch - Misses Per Second
This is the number of instruction line prefetch requests (streaming and
non-streaming) that miss the L2 cache per second.
• Dfetch - Misses Per Second
This is the number of instruction line demand requests that miss the L2 cache per
second.
• Data - Misses Per Second
This is the number of data (load and store) requests that miss the L2 cache per
second.
• Writebacks Per Second
This is the total number of L2 cache writebacks (L3 hit and miss) per second.
• Total - Misses Per Kinst
This is the total number of L2 cache misses per 1000 retired instructions, including
nops and predicated off instructions. It includes instruction prefetch misses,
instruction demand misses, and data misses.
• Pfetch - Misses Per Kinst
This is the number of instruction line prefetch requests (streaming and
non-streaming) that miss the L2 cache per 1000 retired instructions, including nops
and predicated off instructions.
• Dfetch - Misses Per Kinst
This is the number of instruction demand requests that miss the L2 cache per 1000
retired instructions, including nops and predicated off instructions.
• Data - Misses Per Kinst
This is the number of data (load and store) requests that miss the L2 cache per
1000retired instructions, including nops and predicated off instructions.
• Load - Misses Per Kinst
This is the number of load operations that miss the L2 unified cache per 1000 retired
instructions, Uncache loads and semaphore operations are excluded from this
metric.
• Store - Misses Per Kinst
This is the number of store operations that miss the L2 unified cache per 1000
retired instructions, including nops and predicated off instructions. Uncache stores
and semaphore operations are excluded from this metric.
l2cache Event Set 325