HP Caliper User's Guide
• Total - Misses Per Kinst
This is the number of demand instruction cache line accesses that and instruction
prefetch cache lines accesses that miss the L1 instruction cache and ISB per 1000
instructions retired.
• Dfectch - Misses Per Kinst
This is the number of demand instruction cache line access that miss the L1
instruction cache and ISB per 1000 instructions retired.
• Pfetch - Misses Per Kinst
This is the number of streaming and non-streaming prefetches that miss the L1I
cache and ISB per 1000 instructions retired. These are the prefetches that will
actually be issued to the L1 and possibly outer levels of the cache hierarchy,
potentially culminating in a request to memory.
• Ifills Per Kinst
This the number of (64 byte) lines per 1000 instruction retired that are moved from
the ISB to the L1I cache. For the Itanium 2 family of processors (McKinley, Madison,
and Deerfield), this should be approximately equal to the number of ISB Lines per
1000 instructions retired.
• ISB Lines Per Kinst
This is the number of cache line chunks (64 bytes) that were delivered from the L1
cache and beyond to the the ISB per 1000 instructions retired. For the Itanium 2
family of processors (McKinley, Madison, and Deerfield), this should be
approximately equal to the L1I cache fill rate.
• %ISB Line Usage
This is the percentage of ISB lines that are actually delivered to the L1I cache. For
the Itanium 2 family of processors (McKinley, Madison, and Deerfield), this fraction
will be at or slightly less than 100%.
• %Miss - All
This is the percentage of the total misses (instruction demand fetch misses and
instruction prefetch misses) out of the total number of L1 instruction accesses
(instruction demand fetch and instruction prefetch). The prefetches include both
streaming and non-streaming prefetches.
• %Miss - Dfetch
This is the percentage of the number of demand instruction fetch misses out of the
total instruction demand fetch accesses.
• %Miss - Pfetch
This is the percentage of the number of instruction prefetch misses out of the total
number of instruction prefetch requests. The instruction prefetch count includes
streaming and non-streaming prefetches.
l1icache Event Set 323