HP Caliper User's Guide

l1icache Event Set
The l1icache event set provides information on L1 instruction cache miss rates for
both demand fetches and prefetches.
If you use this event set, the default is to make the measurements irrespective of CPU
operating state (that is, user, system, or interrupt states). By default, the idle state is
not included in the measurement. You can use command-line options to limit the scope
of the measurement. Specifically, you can:
Limit measurement to a specific privilege level: -m
event_set[:all|user|kernel]
Include idle: --exclude-idle False
Exclude the interruption state: --measure-on-interrupts off
Only measure the interruption state: --measure-on-interrupts only
The event per kinst (event per 1000 instructions) metrics are computed using all
instructions retired. This includes nops, predicated off instructions, failed speculation
and instructions and associated recovery code as well as the architecturally visible
instruction. You can eliminate idle loops effects by using the command-line option
--exclude-idle True (which is the default). The effects of failed speculative
operations and TLB misses cannot be directly eliminated, but you can get an estimate
of the impact of events from the cspec, dspec, and tlb event sets. You can use the
cpi event set to obtain the fraction of all instructions retired that have an architecturally
visible result, except for predicated off branches, which are counted as useful instructions
(non-taken branch) by the Itanium 2 PMU.
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take
into account any command-line options you might use.
The metrics are:
Total - Misses Per Sec
This is the number of demand instruction cache line accesses and instruction
prefetch cache lines accesses that miss the L1 instruction cache and ISB per second.
Dfetch - Misses Per Sec
This is the number of demand instruction cache line accesses that miss both the
L1 instruction cache and the ISB.
Pfetch - Misses Per Sec
This is the number of streaming and non-streaming prefetches that miss the L1I
cache and ISB per second. These are the prefetches that will actually be issued to
the L1 and possibly outer levels of the cache hierarchy, potentially culminating in
a request to memory.
322 Event Set Descriptions for CPU Metrics