HP Caliper User's Guide

l1dcache Event Set
The l1dcache event set provides information on L1 data cache miss rates for read
misses.
The L1 data cache (L1D cache) is special in that it does not handle all types of memory
references. In particular, the L1D cache does not handle floating-point loads,
semaphores, lfetch instructions and VHPT loads. The L1D cache is also a write-through,
non-store allocate cache. Thus, the only operations that access the L1D are integer loads,
RSE loads, and load checks. The metrics reported only consider the operations that
actually access the L1D cache.
If you use this event set, the default is to make the measurements irrespective of CPU
operating state (that is, user, system, or interrupt states). By default, the idle state is
not included in the measurement. You can use command-line options to limit the scope
of the measurement. Specifically, you can:
• Limit measurement to a specific privilege level: -m
event_set[:all|user|kernel]
• Include idle: --exclude-idle False
• Exclude the interruption state: --measure-on-interrupts off
• Only measure the interruption state: --measure-on-interrupts only
The event per kinst (event per 1000 instructions) metrics are computed using all
instructions retired. This includes nops, predicated off instructions, failed speculation
and instructions and associated recovery code as well as the architecturally visible
instruction. You can eliminate idle loops effects by using the command-line option
--exclude-idle True (which is the default). The effects of failed speculative
operations and TLB misses cannot be directly eliminated, but you can get an estimate
of the impact of events from the cspec, dspec, and tlb event sets. You can use the
cpi event set to obtain the fraction of all instructions retired that have an architecturally
visible result, except for predicated off branches, which are counted as useful instructions
(non-taken branch) by the Itanium 2 PMU.
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take
into account any command-line options you might use.
The metrics are:
• Total - Misses per Sec
This is the total number of L1D cache misses per second.
• NON RSE - Misses per Sec
This is the number of non-RSE L1D cache misses per second.
• RSE - Misses per Sec
This is the number of RSE load L1D cache misses per second.
320 Event Set Descriptions for CPU Metrics