HP Caliper User's Guide

These reports show data associated with a cache line on the same row as the first
instruction of the cache line. Each set of instructions that make up a cache line are
preceded and followed by a row of dashes (“- - - -”). The cache lines shown might not
be contiguous.
Non-contiguous cache lines are separated by a row of tildes (“~ ~ ~ ~”).
How Instruction TLB Metrics Are Obtained
HP Caliper obtains instruction TLB metrics from the processor's performance
monitoring unit (PMU).
Exact counts are obtained from the PMU's performance monitor configuration
(PMC)/performance monitor data (PMD) register pairs. Sampled instruction TLB
metrics are obtained from the PMU's instruction event address register (I-EAR).
HP Caliper takes samples every Nth instruction TLB miss, where N is defined in the
itlb measurement configuration file in the HP Caliper home directory config
subdirectory. At each sample point, HP Caliper records both the cache line that resulted
in an instruction TLB miss and the level of the TLB hierarchy that satisfied the miss
(L2 instruction TLB, HPW, or software). You can override the value in the measurement
configuration file by using the -s option.
HP Caliper attributes samples for a given cache line to the function associated with the
start address of the cache line. Because cache lines can cross function boundaries, data
attributed to functions will not always be completely accurate. However, only cache-line
data at the boundaries of the function are potentially misattributed.
Frequent sampling increases HP Caliper's perturbation of your application. In the
extreme case of taking one sample for each TLB miss event, the kernel will trap on
every event, making the resulting data of limited, if any, value.
286 Descriptions of Measurement Reports