HP Caliper User's Guide

L1I_READS Number of demand fetch reads to the L1
instruction cache (32-byte chunks). For more
information, see L1I_READS .
L2I_DEMAND_READS Number of instruction requests to L2 instruction
cache due to L1 instruction cache demand fetch
misses. This includes the number of demand
fetches that miss both the L1 instruction cache
and the ISB, regardless of whether they hit or
miss in the RAB.
L2I_PREFETCHES Number of prefetch requests issued to the L2
instruction cache. This includes streaming and
non-streaming prefetches.
L2I_READS.ALL.ALL Number of cacheable code reads handled by the
L2 instruction cache.
L2I_READS.MISS.ALL Number of demand fetch and prefetch misses in
cacheable code reads handled by the L2
instruction cache. This only includes the primary
misses.
L2I_READS.MISS.DMND Number of demand fetch misses in cacheable
code reads handled by the L2 instruction cache.
This includes the primary misses.
% of Cycles lost due to all stalls
(lower is better)
Percentage of cycles lost due to all stalls.
% of Cycles lost due to Front end
stalls (ICACHE, ITLB and branch
execution)
Percentage of cycles lost due to instruction cache,
instruction translation lookaside buffer, and
branch execution stalls.
L1 instruction cache references Number of L1 instruction cache references.
L1 instruction cache misses Number of L1 instruction cache prefetch and
demand fetch misses.
L1 instruction cache miss percentage Percentage of L1 instruction demand fetch and
prefetch that are misses.
L1 instruction prefetch miss
percentage
Percentage of L1 instruction prefetches that are
misses.
L1 instruction demand miss
percentage
Percentage of L1 instruction demand fetches that
are misses.
L2 instruction demand misses Number of L2 instruction demand fetch misses.
L2 instruction prefetch misses Number of L2 instruction prefetch misses.
L2 instruction cache miss percentage Percentage of L2 instruction demand fetches and
prefetches that are misses.
L1 instruction cache misses per 1000
instructions retired
Number of instructions retired per L1 instruction
cache miss.
278 Descriptions of Measurement Reports