HP Caliper User's Guide

both the L1 instruction cache and the ISB
regardless of whether they hit or miss in the RAB.
If a demand fetch does not have an L1 instruction
TLB miss, L2_INST_DEMAND_READS and
L1_READS line up in time. If a demand fetch
does not have an L2 instruction TLB miss,
L2_INST_DEMAND_READS follows L1I_READS
by 3-4 clocks (unless a flushed iwalk is pending
ahead of it, which will increase the delay until
the pending iwalk is finished).
If demand fetch has an L2 instruction TLB miss,
the skew between L2_INST_DEMAND_READS
and L1I_READS is not deterministic.
L1I_PREFETCHES Provides information about the number of issued
L1 cache line prefetch requests (64 bytes/line).
The reported number includes streaming and
non-streaming prefetches. Hits and misses in L1
instruction cache are both included.
L1 Instruction Cache Read Misses Number of L1 instruction cache read misses.
L1 Instruction Cache Demand Miss
Percentage
Percentage of demand fetch reads that missed.
Total L1 Instruction Cache
References
Sum of demand fetch reads and L1 cache line
prefetch requests.
Metrics for Integrity Servers Dual-Core Itanium 2 and Itanium 9300 Quad-Core Processor Systems
BACK_END_BUBBLE.ALL Full Pipe Bubbles in Main Pipe due to all causes.
This is the number of cycles lost (stall cycles) due
to any of five possible events (FPU/L1D, RSE,
EXE, branch/exception, or the front-end).
BACK_END_BUBBLE.FE Full Pipe Bubbles in Main Pipe due to front end.
This is the number of cycles lost (stall cycles) due
to instruction cache ITLB and branch execution
stalls.
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
IA64_INST_RETIRED Number of retired IA–64 instructions. The count
includes predicated on and predicated off
instructions, and nops, but excludes
hardware-inserted RSE operations.
L1I_PREFETCHES Number of issued L1 cache line prefetch requests
(64 bytes/line). For more information, see
L1I_PREFETCHES.
icache Measurement Report Description 277