HP Caliper User's Guide

following: 100 * (1– L2DTLB_MISSES /
DATA_REFERENCES).
Percentage of Data References
Covered by the HPW
Percentage of data references that were satisfied
by the hardware page walker (HPW). This is
calculated as the following: 100 *
(DTLB_INSERTS_HPW / DATA_REFERENCES).
Percentage of Data References
Covered by Software Trap
Percentage of data references that were serviced
by the software trap handler for the TLB misses
fault. This is calculated as the following: 100 *
((L2DTLB_MISSES - DTLB_INSERTS_HPW) /
DATA_REFERENCES).
Percentage of L2 DTLB Misses
Covered by the HPW
Percentage of L2 DTLB misses that were serviced
by the hardware page walker (HPW). This is
calculated as the following: 100 *
(DTLB_INSERTS_HPW / L2DTLB_MISSES).
Metrics for Integrity Servers Dual-Core Itanium 2 and Itanium 9300 Quad-Core Processor Systems
BACK_END_BUBBLE.ALL Number of cycles when the back end of the
pipeline was stalled. This is the number of cycles
lost (stall cycles) due to any of five possible
events (FPU/L1D, RSE, EXE, branch/exception,
or the front end).
BE_EXE_BUBBLE.FRALL Full Pipe Bubbles in Main Pipe due to FR/FR or
FR/load dependency stalls. This is the number
of cycles lost (stall cycles) due to FR/FR or
FR/load dependency stalls.
BE_EXE_BUBBLE.GRALL Full Pipe Bubbles in Main Pipe due to GR/GR or
GR/load dependency stalls. This is the number
of cycles lost (stall cycles) due to GR/GR or
GR/load dependency.
BE_EXE_BUBBLE.GRGR Full Pipe Bubbles in Main Pipe due to GR/GR
dependency stalls. This is the number of cycles
lost (stall cycles) due to GR/GR dependency
stalls.
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
DATA_REFERENCES The number of data memory references issued
into memory pipeline. Includes check loads,
non-cacheable accesses, RSE operations,
semaphores, and floating-point memory
references. The count includes wrong path
operations but excludes predicated off
operations. This event does not include VHPT
memory references.
dtlb Measurement Report Description 261