HP Caliper 5.7 User Guide (769153-001, March 2014)

Example Command Line for Text Report
$ caliper itlb -o reports/itlbm.txt ./matmul
Example Command Line for CSV Report
$ caliper itlb --csv csvout ./matmul
itlb Metrics Summed for Entire Run
This section describes the metrics summed over the entire run of your application under HP Caliper.
Metrics for Integrity Servers Itanium 2 Systems
L1I_READS The number of data memory read references issued into the
memory pipeline that are serviced by L1D (only integer
loads), RSE loads, L1-hinted loads (L1D returns data if it hits
in L1D but does not do a fill), and check loads (ld.c).
Non-cacheable reads, VHPT loads, semaphores,
floating-point loads, and lfetch instructions are not counted
here because L1D does not handle these. The count includes
wrong path operations but excludes predicated off
operations.
ITLB_MISSES_FETCH.L1ITLB Number of L1 instruction TLB misses for demand fetch.
Misses are counted even if the L1 instruction TLB is not
updated for an access (non-cacheable/nat page/not present
page/faulting/some flushed), it will be counted here.
ITLB_MISSES_FETCH.L2ITLB Number of L1 instruction TLB misses that also missed in the
L2 instruction TLB.
Total L1 Instruction TLB References Total number of L1 instruction TLB references.
L1 Instruction TLB Miss Ratio Ratio of L1 instruction TLB misses to Total L1 instruction TLB
references.
Metrics for Integrity Servers Dual-Core Itanium 2 and Itanium 9300 Quad-Core Processor Systems
BACK_END_BUBBLE.ALL Number of cycles when the backend of the pipeline was
stalled. This is the number of cycles lost (stall cycles) due to
any of five possible events (FPU/L1D, RSE, EXE,
branch/exception, or the frontend).
BACK_END_BUBBLE.FE Full Pipe Bubbles in Main Pipe due to frontend. This is the
number of cycles lost (stall cycles) due to ICACHE ITLB and
branch execution stalls.
BE_LOST_BW_DUE_TO_FE.ALL Number of invalid bundles at the exit from Instruction Buffer
only if the backend is not stalled for other reasons.
BE_LOST_BW_DUE_TO_FE.IMISS Number of invalid bundles at the exit from Instruction Buffer
due to instruction cache miss stalls (only if the backend is
not stalled for other reasons).
BE_LOST_BW_DUE_TO_FE.TLBMISS Number of invalid bundles at the exit from Instruction Buffer
due to instruction TLB miss stalls (only if the backend is not
stalled for other reasons).
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
IA64_INST_RETIRED Number of retired IA-64 instructions. The count includes
predicated on and predicated off instructions and nops, but
excludes hardware-inserted RSE operations.
ITLB_MISSES_FETCH.L1ITLB Number of L1 ITLB misses for demand fetch.
ITLB_MISSES_FETCH.L2ITLB Number of L2 ITLB misses for demand fetch.
220 Descriptions of Measurement Reports