HP-UX 11i v3 Memory Management Subsystem

Application programs can use the memory hints, possibly in conjunction with the processor binding facility offered

through the

mpctl(2) interface, to attempt to gain favorable processor to memory alignment on NUMA platforms.

Such attempts are complicated by the following considerations:

• dynamic platform reconfiguration events can cause processors, memory ranges, or entire localities to change

composition or disappear entirely

• other applications running on the same server may also attempt to do memory placement and/or processor

binding, which can cause imbalances in resource utilization

• in LORA mode, HP-UX automatically strives to give each application the best possible processor to memory

alignment on a continuing basis

For those reasons, applications might do better to forego memory placement hints altogether, and allow the

operating system to do its own placement. Alternatively, the system administrator can use the

numa_policy(5)

tunable parameter to govern application memory placement on a system-wide basis.

Large Virtual Pages

At the basic level, the HP-UX memory management subsystem always manages memory in units of the system base

page size. Applications may work with objects that are much larger than that base page size. In those cases, it

may be more efficient to aggregate a range of base pages into a "superpage", also called a "large page". This

efficiency is most important in the utilization of the hardware resource called the translation lookaside buffer (TLB).

HP-UX automatically recognizes situations in which large pages are beneficial and manipulates them accordingly.

The system administrator can influence the kernel's behavior in this regard through the

vps_ceiling(5),

vps_chatr_ceiling(5), and vps_pagesize(5) tunable parameters.

In some cases, use of variable pages that are too large can cause inefficiencies, for example, if a large memory

object is accessed in a sparse manner. Each individual application can provide hints to the kernel as to the best

page size through the

chatr(1) command. In particular, the +pi and +pd options can be used to suggest the

page sizes for code and data, respectively.

For more information

vPars Administrator’s Guide http://docs.hp.com/en/T1335-90104/index.html

Tunable Base Page Size whitepaper http://docs.hp.com/en/14670/ENW-TBPS-TW.pdf

LORA whitepaper

http://www.docs.hp.com/en/14655/ENW-LORA-TW.pdf

HP GlancePlus product information

Adaptive Address Space whitepaper

http://www.hp.com/go/glance

http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/aas_white_paper.pdf

HP-UX Performance Cookbook

http://h21007.www2.hp.com/portal/download/files/unprot/devresource/Docs/TechPapers/UXPerfCookBook.pdf

HP Superdome 2 Partitioning Administrator Guide