Adaptive Address Space Whitepaper

glossary

(simplified)

for more

information

AAS: Adaptive Address Space. The feature being discussed in this paper.

Aliasing: In this paper, aliasing refers to the condition when two or more unique

virtual addresses translate to the same physical address. All aliased virtual

addresses can be used to access the same data.

BSS: Block Started by Symbol. The section of a program’s data which is used to

store global data that is not initialized explicitly by the programmer. (Implicitly

initialized to 0).

MGAS: Mostly Global Address Space. This is the default address space layout on

HP-UX.

MPAS: Mostly Private Address Space. This is the new type of address space

layout that is introduced by the AAS project.

RISC: Reduced Instruction Set Computer. A computer architecture that reduces

chip complexity by using simpler instructions.

RSE: Register Stack Engine. Traditional processor architectures require spilling

and filling of registers during function call /return. On newer, RISC architectures,

a register stack engine avoids this via compiler controlled renaming of general

registers. For details, refer to the IA-64 Architecture Software Developer’s

Manual.

TLB: Translation Look-aside Buffer. A small table in the processor’s Memory

Management Unit that contains translations from virtual address to physical

addresses.

For more information on memory-windows, go to

http://docs.hp.com/hpux/onlinedocs/os/memwn1_4.pdf

For more information on the linker and other developer tools, go to

http://docs.hp.com/hpux/dev/index.html#Developer%20Tools%20and%20Librari

For more information on the IPF architecture, see the Intel® IA-64 Architecture

Software Developer's Manual.

For more information on the following, see the relevant HP-UX manual pages:

• mmap(2)

• mprotect(2)

• shmat(2)

• shmget(2)

• ld(1)

• cc(1)

• chatr(1)