HP-UX HB v13.00 Ch-21 - Itanium
HP-UX Handbook – Rev 13.00 Page 6 (of 35)
Chapter 21 Itanium Architecture (IA)
October 29, 2013
To provide more on-chip resources, Intel’s Itanium based processors capitalize on both the
strengths of explicit parallelism and the savings in chip space that the 64-bit ISA provides.
Itanium based processors have massive resources, with 128 general (integer) registers, 128
floating-point registers, 64 predicate registers, 8 branch registers and 128 control registers. In
contrast, today’s RISC based processors typically have only 32 general registers and are
therefore forced to use register renaming or some other mechanism to create the resources
necessary for parallel execution. In Itanium, the functional units attached to the large register file
can also be replicated, making Itanium inherently scalable over a wide range of implementations.
Of course, since replicated functional units increase the machine width, performance can be
increased correspondingly. And with the more sizable caches and the many more read and write
ports afforded to memory, the speed of Itanium based processors is no longer limited by the
memory latency problems of traditional processors.
A more detailed description of the EPIC features including a code example can be found at
http://www.software.hp.com/products/IA64/arch.html.
The Itanium processor family (IPF)
Intel announced several generations of the Itanium Processor Family (IPF). The following IPF
processors are available as of today.
Feature
1
st
generation
2
nd
generation
Itanium
McKinley
Madison
CPU clock speeds
733/800MHz
900/1000MHz
1.3GHz/1.5GHz
System Bus
Width
64 bit
128 bit
128 bit
speed/transactions
133MHz/266 MT/s
200MHz/400 MT/s
200MHz/400 MT/s
Bandwidth
2.1 GB/s
6.4 GB/s
6.4 GB/s
Width
bundles per clock
2
2
2
integer units
4
6
6
loads/stores per clock
2 load or stores
2 loads and 2 stores
2 loads and 2 stores
issue ports
9
11
11
Caches (*)
level 1 size/latency
2x 16K / 2 cycles
2x 16K / 1 cycles
2x 16K / 1 cycles
level 2 size/latency
96K / 12 cycles
256K / 5-7 cycles
256K / 5-7 cycles
level 3 size/latency
2-4MB off die
20 cycles
1.5-3MB on die
12-15 cycles
3-6MB on die (*)
14-17 cycles
level 3 bandwidth
11.7 GB/s
32 GB/s
48 GB/s
Addressing
Physical
44 bit
50 bit
50 bit
Virtual
50 bit
64 bit
64 bit