HP-UX HB v13.00 Ch-21 - Itanium

HP-UX Handbook – Rev 13.00 Page 4 (of 35)
Chapter 21 Itanium Architecture (IA)
October 29, 2013
Introduction
When PA-RISC was released, HP began designing the architecture to replace it. Several years
into the project, HP determined that the economics of microprocessor manufacturing favored
partnership and decided to partner with Intel, the leader in volume IC manufacturing. Intel was
working on their next generation architecture as well, so the timing was perfect. This joint
development combined HP's strengths in system and architecture design with Intel's strengths in
processor design and manufacturing.
Overview of the Itanium Architecture
Traditional microprocessor architectures (CISC and RISC) have fundamental attributes that limit
performance. To achieve higher performance, processors must not only execute instructions
faster, but also execute more instructions per cycle, referred to as “parallel execution”. Greater
parallel execution allows more information to be processed concurrently - thereby increasing
overall processor performance. In traditional architectures, the processor is often underutilized
because of the compiler’s limited ability to organize instructions. Branches (instructions that
change the flow of execution within the program) and memory latency (the time for data to
arrive from memory) compound the already limited ability of today’s processors to achieve
parallel execution.
To overcome these limitations, a new architecture was required. Traditional architectures
communicate parallelism through sequential machine code that “implies” parallelism to the
processor. Intel and HP jointly defined a new architecture technology called EPIC (Explicitly
Parallel Instruction Computing) named for the ability of the software to extract maximum
parallelism (potential to do work in parallel) in the original code and “explicitly” describe it to
the hardware. Intel and HP have jointly defined a new 64-bit Instruction Set Architecture (ISA),
based on EPIC technology, which Intel has incorporated into Itanium, Intel’s 64 bit
microprocessor architecture. The new 64 bit ISA takes an innovative approach combining
explicit parallelism with techniques called predication and speculation to progress well beyond
the limitations of traditional architectures. The new architecture is called Itanium™, formerly
known as IA-64.
Main features of EPIC
The main features of EPIC are explicit parallelism, predication and speculation.
Explicit parallelism
In traditional architectures like RISC the processor receives a sequential stream of instructions
from the compiler and must reorder the instructions to prevent functional units from being
idle. The processor can only reorder a small, fixed number of instructions. A particular