HP-UX HB v13.00 Ch-08 - Crash Dumps

HP-UX Handbook – Rev 13.00 Page 8 (of 38)
Chapter 08 Crash Dumps
October 29, 2013
reflection of the registers state in PIM since the information was copied from it. There are rare
times when rpb values may not seem 'right'. If this is the case then it is better to use the register
values in the PIM data as starting point for analysis. Some interesting registers are:
gr02 Return Pointer (rp)
gr30 Stack Pointer (sp)
cr17 Interruption Instruction Address Space Queue (pcsq)
cr18 Interruption Instruction Address Offset Queue (pcoq)
cr19 Interruption Instruction Register (iir)
cr20 Interruption Space Register (isr)
cr21 Interruption Offset Register (ior)
cr22 Interruption Processor Status Word (ipsw)
cr23 External Interrupt Request Register (eirr)
cr15 External Interrupt Enable Mask (eirr)
Save state structure
The save_state structure is used by the interrupt (ihandler) and trap (thandler) handlers to
temporarily store away processor state (general, control, space and interruption registers) so that
these handlers can safely reuse the registers. It will also allow the handlers to return to the point
of interruption by restoring these register values from the save_state. The save_state structure
(together with a frame marker) is typically allocated on the Interrupt Control Stack (ICS) or
kernel stack.
Most of the processor registers are saved. However, some registers are not saved because they
are irrelevant when returning to the point of interruption. Since these interrupt and trap handlers
are executed frequently, it is crucial for performance reasons to save only what is necessary.
RPB structure
Every crash event will create a corresponding RPB structure to contain the processor state at the
time of HPMC, TOC or panic. This register state allows us to understand what is happening at
that point in time as well as provides a starting point for the stack unwind. The rpb structures are
stored in a pre-allocated area in kernel static data area.
Unlike the save_state structure, the rpb structure will contain a more complete save of all the
processor registers. For example, the cr16 interval timer is saved in the rpb but not in the
save_state structure. We can afford to save more registers in rpb since it is created during the
crash path which is not a performance sensitive code path.
Crash event flowchart
Here is a diagram summarizing the above: