HP Mainframe Connectivity Design Guide

P9500 mainframe addressing of volumes
Table 63 (page 106) lists the maximum values for P9500 mainframe configurations per CU.
Table 63 Maximum values for P9500 mainframe configurations
2105-F20 emulation2107 emulationItem
64255CU image per DKC
2,0482,048Channel images per CU image
1,0241,024Channel images per CU image per CU port
131,072522,240Channel images per Logical DKC
65,536261,120Logical paths per CU port
131,072522,240Logical paths per Logical DKC
16,38465,280Number of devices
9696Buffer to Buffer Credit Count per port
480480Concurrent I/Os per CU port
The number of logical paths that can be configured on the mainframe per FICON CHPID and
control unit (CU or LCU) varies depending on the CU type being emulated in the P9500, as
indicated in Table 64 (page 106). These are mainframe HCD configuration maximums, not P9500
configuration maximums.
Table 64 FICON logical path configurations
Maximum number of
logical paths per LCU
Maximum number of
logical paths per
FICON CHPID
Maximum number of
LDEVs per LCUCUADD range
DASD
nl
emulation type
256256
256x'00' to x'FF'
2105-F20
5122,0482107
GDPS/PPRC and GDPS/XRC command support
The P9500 storage system can be integrated into a GDPS/PPRC or GDPS/XRC environment. The
GDPS features that are supported depend on the P9500 storage system model and purchased
licenses. For more information, contact an HP storage representative.
Parallel access volumes
PAVs enable a single LPAR to issue multiple I/O requests in parallel to a disk volume. Volumes
with a base address contain data. PAVs are alias addresses assigned to the volume, in addition
to the volume's base address. Therefore, multiple addresses can point to the same volume and
data, allowing I/O operations to run concurrently with the same volume. For example, the mainframe
can issue up to four I/O operations concurrently to a volume that has one base address and three
PAV addresses.
PAV addresses are included in the total number of addresses (volumes) that the P9500 storage
system supports. Table 65 (page 106) lists the number of PAVs supported for each base address in
a P9500 storage system.
Table 65 P9500 PAV support
Number of PAVs per base addressCU typeStorage system
2552105-F20P9500
106 P9500 storage system rules