Technologies for the ProLiant ML570 G4 and ProLiant DL580 G4 servers

Figure 5. Interleaving between the two channels of memory: 64-bits go to memory controller (channel) 1, the next
64 bits to go to memory controller 2, and so on.
XMB rank interleaving
Rank interleaving within the XMB groups several ranks of memory together so that cache lines are
sequentially read or written across the entire group. For example, suppose that bank A and bank B
are interleaved together. (In this example, all contain single-rank DIMMs, so bank A is equivalent to a
rank.) The first requested cache line would come from bank A DIMMs, the next cache line would
come from bank B DIMMs, the next from bank A DIMMs, and so on (Figure 6). XMB interleaving is
done on 2, 4, or 8 ranks at a time. While bank A is undergoing its refresh cycle, bank B is accessing
memory, and then when bank B is undergoing its refresh cycle, bank A is accessing memory. In this
way, the refresh cycles occur while memory is being accessed.
XMB rank interleaving reduces latencies by allowing multiple memory pages to be open at the same
time, rather than waiting for several cache lines to be read from a single bank.
Figure 6. Rank interleaving: Cache lines are split across a group of memory ranks.
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