Technologies for the ProLiant ML570 G4 and ProLiant DL580 G4 servers

Intel E8501 chipset
The E8501 chipset has a high-availability memory subsystem that consists of the north bridge [TNB]
and the XMB memory controller.
The E8501 chipset supports dual-core versions of Intel processors and has the important feature of
using two separate front side buses to connect to the processors (Figure 2). Each north bridge can
connect to up to four memory boards, and each memory board includes an XMB memory controller
chip. The north bridge connects to each XMB memory controller using a high-speed serial interconnect
(the IMI bus) that allows 6.4 GB/s inbound (for read data signals from the XMB) and 3.2 GB/s
outbound (for write data signals to the XMB). The north bridge uses an in-order (FIFO) queue to
maintain coherency across the dual front-side buses while processing read/write requests.
Figure 2. Block diagram of Xeon MP architecture used in the ProLiant ML570 G4 and DL580 G4 platforms
Each XMB memory controller chip supports two channels of DDR-2 memory. The DDR-2 memory on
each channel operates in lockstep at 400 MHz. The ProLiant ML570 G4 supports six DIMMs per
memory board (three per channel). The ProLiant DL580 supports four DIMMs per memory board (two
per channel), due to physical constraints of the 4U system. For both servers, the maximum memory
supported is 64 GB with 4-GB DIMMs.
Partitioning for electrical isolation
One of the features of a well-designed chipset is the degree to which the silicon is partitioned to allow
different signal areas to be electrically isolated. The E8501 chipset is partitioned so that the front-side
bus interconnects to a partitioned area for the “left” CPU, the “right” CPU, and each memory board
(Figure 3). The XMB is similarly partitioned so that each internal memory controller is isolated
electrically from the other to avoid power noise and crosstalk issues. Avoiding crosstalk and other
6