Technologies for the ProLiant ML570 G4 and ProLiant DL580 G4 servers

Interleaving across XMB memory controllers
Because there are up to four XMB memory controllers (one per memory board), the north bridge
device also splits requested cache lines among all memory controllers. This type of interleaving is
automatically enabled when using more than one memory board (if hot-add is disabled).
For example, if an application requires 40 cache lines of data and the server contains four memory
boards, the north bridge will split those 40 cache lines across the four memory boards in a sequential
fashion: Cache line 1 comes from memory board 1, cache line 2 comes from memory board 2, and
so on (Figure 7). Assuming that rank interleaving is also enabled, the memory controller will read the
fifth cache line from the second rank of DIMMs on memory board 1. Distributing the memory reads
and writes across multiple controllers reduces memory access times for individual controllers and
reduces the likelihood of processors waiting on data.
The north bridge has no mechanism for updating the interleaving scheme on the fly if new memory
boards are added. Therefore, if hot-add memory is enabled, interleaving cannot be done across
memory controllers and it will be disabled.
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Figure 7. Interleaving across XMB memory controllers: The north bridge interleaves the cache lines among the
memory board subsystems (moving down vertically in the schematic). Rank interleaving would then interleave
cache lines horizontally, as depicted with cache line 5.
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The one exception is if all four memory boards are installed and hot-add is enabled: Because the system is
already fully populated with memory boards, the north bridge controller can interleave memory across the XMB
memory controllers.
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