HP ProLiant DL585 Server Technology - Technology Brief

• Node interleaving (SUMA) breaks memory into 4-KB addressable entities. Addressing

starts with address 0 on node 0 and sequentially assigns through address 4095 to node 0,

addresses 4096 through 8191 to node 1, addresses 8192 through 12287 to node 3, and

addresses 12888 through 16383 to node 4. Address 16384 is assigned to node 0 and the

process continues until all memory has been assigned in this fashion.

There is no rule for organizing memory for the best performance of an application because

the difference in latency between the NUMA operation and SUMA operation is small. In

general, a NUMA-aware operating system such as Microsoft Windows, and a NUMA-aware

application such as Microsoft SQL Server will benefit from the NUMA organization. A NUMA-

aware operating system and applications which allocate and de-allocate memory at the

thread level will benefit from the NUMA organization, because the allocation and the

thread will have a tendency to run on the same node. If an application uses a common

allocation thread it will benefit from node interleaving.

The DL585 has, by default, NUMA memory configuration. For those applications that cannot

take advantage of the NUMA architecture, performance may be improved by activating

node interleaving (SUMA). System administrators can activate node interleaving using the HP

ROM-Based Setup Utility (RBSU) provided as part of the ProLiant Essentials Foundation Pack.

I/O subsystem

I/O devices connect to the processor/memory boards via AMD’s HyperTransport

technology links rather than traditional I/O buses. AMD HyperTransport technology links are

capable of signaling with clock speeds of up to 1 GHz, and Double Data Rate (DDR)

memory signaling. Two factors contribute significantly to the signal speed:

• A HyperTransport point-to-point link, which speeds up data transfer by interconnecting all

processors and embedded memory in the system. HyperTransport technology provides a

universal connection designed to reduce the number of buses within the system, to

provide a high-performance link for embedded applications, and to enable highly

scalable multiprocessing systems. In the ProLiant DL585, HyperTransport technology

delivers 8 GB/s processor-to-processor throughput for maximum performance and

scalability.

• Resources do not share an I/O bus, so there is no overhead for bus arbitration.

HyperTransport links can provide an effective throughput of 2.0 gigatransfers per pin-pair

on a link.

The ProLiant DL585 system board has an integrated 1280 x 1024, 16M color graphics

controller with 8 MB of SDRAM video memory on the PCI local bus.

The ProLiant DL585 server contains eight full-length, 64-bit PCI-X slots: Slots 1 and 2 operate

at up to 133 MHz; slots 3 through 8 operate at up to 100 MHz. None of these slots supports

PCI Hot-Plug Technology.

NOTE

The two PCI-X slots running at 133 MHz are limited to adapters with

three PCI functions or less.