HP ProLiant DL585 Server Technology - Technology Brief

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AMD-8000™ series chipset
The ProLiant DL585 server uses the AMD-8000 series chipset with Direct Connect
Architecture and HyperTransport™ technology. HyperTransport is a parallel point-to-point
interconnect that replaces parallel front-side bus technology. Direct Connect architecture
is AMD’s designation for the coherent HyperTransport connection between processors. It
eliminates the bottlenecks inherent in front-side bus technology by integrating the memory
controller into the AMD Opteron chip and directly connecting CPUs to the IO subsystem
and other processors.
The chipset consists of the following key components:
• AMD-8131 HyperTransport PCI-X tunnels, Three are used in the DL585.
• AMD-8111 HyperTransport I/O hub (south bridge)
The AMD Opteron includes the AMD64 instruction set architecture, which enables the
ProLiant DL585 server to support both 32-bit and 64-bit applications running
simultaneously⎯with no performance penalty. Unlike the Itanium processor family (IPF)
which requires the mode of operation to switch between x86 and IPF modes, the AMD64
instruction set is an extension of the x86 instruction set and requires no mode change to
support 64-bit instructions.
Dual-core technology
A dual-core processor is a single die that contains two CPU cores, each with its own 1-MB
L2 cache. The dual-core technology leverages the same memory and HyperTransport
technology resources available in the single-core processors. Dual-core technology
delivers high performance and reduced latency for multithreaded and multitasking
environments while maintaining a similar power requirement to single-core processors.
Dual-core processors generally run at one or two clock-steps below the current top speed
single-core version, thereby maintaining the same power envelope. For more details about
AMD processor architecture, refer to the HP white paper “The AMD processor roadmap for
HP ProLiant servers,” available at this URL:
HTUhttp://h20000.www2.hp.com/bc/docs/support/SupportManual/c00428708/c00428708.pdfUHT
Processor/memory boards
The ProLiant DL585 server supports up to four processor/memory boards (2 or 4 are the only
valid configurations supported). Each of these boards includes an AMD Opteron 800 series
processor running at up to 2.4 GHz for dual-core processors or up to 2.8 GHz, for single-core
processors. There is an integrated memory controller that operates at CPU core frequency,
a 144-bit-wide memory bus, and eight DIMM slots supporting up to 128 GB of memory,
assuming 4 GB DIMMs.
The Opteron processors operate at core speeds of up to 2.8 GHz. Each processor supports
64-KB integrated Level 1 (L1) instruction cache, 64-KB integrated L1 data cache, and 1-MB
L2 cache. The processors support IA-32 and the AMD-64 instruction set for running 64-bit
applications.
Memory subsystem
Typical multiprocessor PC server architecture connects IA-32 processors to memory DIMMs
by means of a north bridge chip. The north bridge is a memory controller and bridge to the
I/O expansion interface. AMD Opteron architecture differs from typical multiprocessor
server architecture in that AMD’s north bridge is integrated into the Opteron 800 series
processor to boost performance. Performance is enhanced by eliminating bus contention
created when memory and I/O paths pass through a typical, non-integrated north bridge.
Because the memory controller is integrated onto the processor chip, memory latency is
greatly reduced.