HP ProLiant DL585 G7 server technology

Memory technologies
In AMD Opteron architecture, the processor chip has an integrated memory controller. The on-die
memory controller reduces memory latency by eliminating the bus contention between memory and
I/O cycles found on a typical Northbridge processor.
In addition, with each processor containing its own memory controller, the aggregate bandwidth for
system-accessible memory is scalable in multi-processor systems such as the HP ProLiant DL585 G7.
The Opteron 6100 series processor includes two memory controllers and supports four memory
channels of DDR3 memory with bus speeds of up to 1333 MHz. This architecture doubles the memory
capacity compared to previous generations of AMD Opteron processors.
The architecture supports up to four processors and 48 DIMMs, allowing the maximized memory
footprint of 512 Gb for an optimal price.
The DL585 G7 supports single-, dual- or quad-rank RDIMMs. In addition, it supports ECC and On-Line
Spare memory.
The load on the memory bus determines the maximum memory bus speed. The processor controls the
memory bus speed according to the rules shown in Table 2.
Table 2. Memory configuration options in the DL585 G7
DIMMs per processor Maximum memory speed
2, 4 1333 MHz
6 1066 MHz
8 800 MHz
For more information on the topic of DDR3 memory visit:
http://
h20000.www2.hp.com/bc/docs/support/SupportManual/c02126499/c02126499.pdf
I/O technologies
The HP ProLiant DL585 G7 server supports two expansion bus technologies, PCI Express and PCI-X.
With the DL 585 G7 architecture, you can install a PCIe expansion card into any slot it fits, and it will
work correctly.
The server base configuration supports five PCI Express slots, three of which are full-length x8 slots.
The remaining two are full-length x16 slots.
Two optional I/O expansion boards are available, adding an additional six slots for expansion. One
option adds two full-length x16 PCIe slots and four full-length x8 PCIe slots.
The other option adds one full-length x16 PCIe slot, two full-length x8 PCI-e slots, one full-length x4
PCIe slot, and two 64-bit, 100 MHz, full-length PCI-X slots.
Since the processors and their associated chipsets split the management of PCIe handling, you can
achieve optimal performance by balancing the load of multiple PCIe cards across the HyperTransport
links. This reduces the likelihood of applications associated with high I/O traffic causing bottlenecks.
Refer to the Figure 2 block diagram for details and to Table 3 and Table 4 for slot assignments.
Shaded table rows are slot assignments occupied by either of the two possible expansion kits.
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