HP ProLiant DL585 G5/G6 server technology

Figure 4. Block diagram of DL585 G5/G6 architecture
Memory technologies
Typical multiprocessor PC server architecture connects IA-32 processors to memory DIMMs by means
of a north bridge chip, which provides the memory controller function. However, in AMD Opteron
architecture, the memory controller is integrated into the processor chip for enhanced performance.
The on-die memory controller reduces memory latency by eliminating the bus contention between
memory and I/O cycles on a typical north bridge. In addition, with each processor containing its own
memory controller, the aggregate bandwidth for system-accessible memory is scalable in multi-
processor systems such as the DL585.
The Opteron processor supports dual-channel memory. Two 64-bit-wide memory channels operate in
parallel to provide a 128-bit interface. Since the DL585 supports dual-width memory channels,
DIMMs must be installed in pairs.
By default, ProLiant DL585 memory operates in a linear configuration. This provides optimum
performance for Microsoft Windows operating systems and for many applications, such as Microsoft
SQL Server. Linear memory is allocated and de-allocated at the thread level, and access is defined on
all nodes sequentially. Sequential addresses are assigned to all memory locations starting on node 0,
then to all locations on node 1, and so on, until memory locations on all nodes have been assigned.
For those applications that cannot take advantage of linear memory configuration, ProLiant DL585
performance may be improved by activating node interleaving. System administrators can activate
node interleaving using the HP RBSU. Node-interleaving breaks memory into 4-KB addressable
entities. Applications that use a common allocation thread will benefit from node interleaving.
The ProLiant DL585 G5 and G6 support PC2-6400 and PC2-5300 DDR2 memory. As more DIMMs
are installed on a single memory controller (that is, per processor), the memory bus for that processor
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