HP ProLiant DL585 G5 server technology, 1st edition

processors with an additional 16-bit, 1-GHz HyperTransport connection. In addition to supporting
system devices and USB ports, the 2200 offers an additional PCIe x4 slot and two PCIe x8 slots.
Memory technologies
Typical multiprocessor PC server architecture connects IA-32 processors to memory DIMMs by means
of a north bridge chip, which provides the memory controller function. However, in AMD Opteron
architecture, the memory controller is integrated into the processor chip for enhanced performance.
The on-die memory controller reduces memory latency by eliminating the bus contention between
memory and I/O cycles on a typical north bridge. In addition, with each processor containing its own
memory controller, the aggregate bandwidth for system-accessible memory is scalable in multi-
processor systems such as the DL585 G5.
The Opteron processor supports dual-channel memory.
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Two 64-bit-wide memory channels operate in
parallel to provide a 128-bit interface. Since the DL585 G5 supports dual-width memory channels,
DIMMs must be installed in pairs.
By default, memory in the DL585 G5 operates in a linear configuration, which provides optimum
performance for Microsoft Windows operating system and for many applications, such as Microsoft
SQL Server. Linear memory is allocated and de-allocated at the thread level, and access is defined on
all nodes sequentially. Sequential addresses are assigned to all memory locations starting on node 0,
then to all locations on node 1, and so on until memory locations on all nodes have been assigned.
For those applications that cannot take advantage of linear memory configuration, DL585 G5
performance may be improved by activating node interleaving. System administrators can activate
node interleaving using the HP ROM-Based Setup Utility (RBSU) provided as part of the HP ProLiant
Essentials Foundation Pack. Node-interleaving breaks memory into 4-KB addressable entities.
Addressing starts with address 0 on node 0 and assigns sequential addresses through address 4095
to node 0, addresses 4096 through 8191 to node 1, addresses 8192 through 12287 to node 2,
and addresses 12888 through 16383 to node 3. Address 16384 is assigned to node 0, and the
process continues until all memory has been assigned in this fashion. An application that uses a
common allocation thread will benefit from node interleaving.
The DL585 G5 supports PC2-5300 DDR2 memory at 533 MHz and 667 MHz. When more than four
DIMMS are installed on a single memory controller (that is, per processor), the memory bus for that
processor will be clocked down to 533 MHz. Table 1 lists available memory configurations for the
DL585 G5.
Table 1. Memory configuration options in the DL585 G5 with PC2-5300 DIMMs
Max memory
capacity
DIMM size Maximum DIMMs
per processor
Memory
speed
128 GB (256 GB with 8-GB
DIMMs, when available)
512 MB,1 GB,
2 GB, 4 GB
8 533 MHz
64 GB 512 MB, 1 GB,
2 GB, 4 GB
4 667 MHz
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For more information on memory technology, refer to the HP technology brief “Memory Technology Evolution:
An Overview of System Memory Technologies” available at the following URL
http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf
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