HP ProLiant AMD-based 300-series G7 servers

AMD-based 300-series G7 servers support all three memory interleaving technologies. Even though

these technologies are independent of each other, they can operate simultaneously.

Memory bank interleaving

With memory bank

interleaving engaged, data is routed alternately to memory banks through the

common memory channel connecting the DIMM banks and the integrated memory controller.

However, memory bank interleaving does increase the probability that more DIMMs need to be kept

in an active state (requiring more power) since the memory controller alternates between memory

banks and therefore between DIMMs.

The processor node memory controller automatically enables memory bank interleaving under the

following conditions:

• Two single-rank DIMMs per channel result in two way-bank interleaving

• Two dual-rank DIMMs per channel result in four way-bank interleaving

• Two quad-rank DIMMs per channel results in eight-way bank interleaving

• Two dual-rank DIMMs and one quad-rank DIMM results in eight-way bank interleaving (in servers

using three DIMMs per channel)

Memory Channel Interleaving

With memory

channel interleaving, the processor memory controller routes data alternately through

the two available memory channels. The result is that when the memory controller needs to access a

block of logically contiguous memory, the requests are distributed more evenly across the two

channels rather than potentially stacking up in the request queue of a single channel. This alternate

routing decreases memory access latency and increases performance. As with memory bank

interleaving, memory channel interleaving increases the probability that more DIMMs need to be kept

in an active state.

Memory channel interleaving is always active on the AMD 6100-series processor.

Memory node interleaving

With node interleaving, memory c

an be interleaved across any subset of nodes in the multiprocessor

system. Node interleaving breaks memory into 4 KB addressable entities. Addressing starts with

address 0 on node 0 and assigns sequential addresses through address 4095 to node 0, addresses

4096 through 8191 to node 1, addresses 8192 through 12287 to node 2, and addresses 12888

through 16383 to node 3. Address 16384 is assigned to node 0, and the process continues until all

memory has been assigned in this fashion. An application that uses a common allocation thread will

benefit from node interleaving.

Memory node interleaving is disabled by default. Administrators can activate node interleaving using

the RBSU. Node interleaving can only be configured if the memory footprint for both processors

identical.

X8 error correction

In AMD Opteron 6100-series processors, the memory controller supports error correction circuitry

(ECC) for both x4 and x8 DIMMs.

I/O technologies

ProLiant 300-series G7 servers incorporate PCI Express, Serial-Attached SCSI (SAS), and Serial ATA

(SATA) I/O technologies. This server architecture lets administrators add PCI Express-compliant