HP ProLiant 300-series AMD-based G6 server technology

memory interleaving technologies are supported on the ProLiant AMD 300-series G6 servers. These

technologies are independent of each other and can operate simultaneously.

Memory bank interleaving

When memory bank

interleaving is engaged, data is routed alternately to memory banks through the

common memory channel connecting the DIMM banks and the integrated memory controller.

However, memory bank interleaving does increase the probability that more DIMMs need to be kept

in an active state (requiring more power) since the memory controller alternates between memory

banks and therefore between DIMMs.

Memory bank interleaving is automatically enabled on a processor node under the following

conditions:

• DIMMs are installed in identical pairs

• Four single-rank DIMMs are populated per node (4 x 1 GB or 4 x 2 GB for example)

• Two dual-rank DIMMs are populated per node (2 x 4 GB or 2 x 8 GB for example)

• Four dual-rank DIMMs are populated per node (4 x 4 GB or 4 x 8 GB for example)

Using four single-rank DIMMs or two dual-rank DIMMs results in two-way bank interleaving. Using

four dual-rank DIMMs results in 4-way bank interleaving.

DIMMs must be installed in identical pairs. If single and dual ranked DIMMs are mixed on the same

node, bank interleaving will not be enabled. DIMMs must be installed in decreasing capacity with the

largest DIMMs installed in the banks furthest away from each processor.

Memory Channel Interleaving

With memory c

hannel interleaving, data is transferred by means of alternate routing through the two

available memory channels. The result is that when the memory controller needs to access a block of

logically contiguous memory, the requests are distributed more evenly across the two channels rather

than potentially stacking up in the request queue of a single channel. This alternate routing decreases

memory access latency and increases performance. As with memory bank interleaving, memory

channel interleaving increases the probability that more DIMMs need to be kept in an active state.

Memory channel interleaving is always active on the AMD 2400-series processor.

Memory node interleaving

Node interlea

ving allows memory to be interleaved across any subset of nodes in the multiprocessor

system. Node interleaving breaks memory into 4 KB addressable entities. Addressing starts with

address 0 on node 0 and assigns sequential addresses through address 4095 to node 0, addresses

4096 through 8191 to node 1, addresses 8192 through 12287 to node 2, and addresses 12888

through 16383 to node 3. Address 16384 is assigned to node 0, and the process continues until all

memory has been assigned in this fashion. An application that uses a common allocation thread will

benefit from node interleaving.

Memory node interleaving is disabled by default. Administrators can activate node interleaving using

the RBSU. Node interleaving can only be configured if the memory footprint for both processors is the

same.

X8 error correction

In AMD Opteron 2400-series processors, the memory controller supports error correction circuitry

(ECC) for both x4 and x8 DIMMs.