HP ProLiant 300-series AMD-based G6 server technology

Figure 2. The H

yperTransport interconnect is designed to separate memory and I/O traffic and directly attaches

memory to each processor, allowing memory capacity to scale with the number of processors.

HyperTransport can be configured through the R

OM-Based Setup Utility (RBSU). In the RBSU

Advanced Options menu, administrators can use the HyperTransport Selection option to choose HT1

or HT3. HT1 is active by default.

HyperTransport is designed to provide a direct, scalable bandwidth interconnect between the

processor, the I/O subsystem, and the chipset. Due to chipset architecture in ProLiant AMD G6

servers, HT3 supports processor to processor communication, but not I/O operations.

HT Assist

HT Assist™ reduces cache coherence traffic on the HT links. By tracking where data is stored in cache

and guiding the processor directly to the data in the other processors’ caches, HT Assist reduces

cache probe traffic between processors, especially in 4-socket servers. Therefore, HT Assist results in

faster queries that can increase performance for cache-sensitive applications such as database,

virtualization, and compute-intensive applications.

Memory technologies

In the AMD Opteron 2400-series architecture, the memory controller is integrated into the processor

chip to optimize memory performance and bandwidth per CPU. The memory controller reduces

latency inherent in front side bus architectures by eliminating the bus contention between memory and

I/O cycles. AMD's memory bandwidth increases as processors are added to a configuration,

compared to legacy designs that scale poorly because access to main memory is limited by external

northbridge chips.