HP ProLiant Intel-based 100-series G6 servers

Figure 1. Blo
ck diagram of three-level cache hierarchy for Intel Xeon 5500 Series processors
The Level 3 cache is shared and inclusive, which means that it du
plicates the data stored in the Level
1 and Level 2 caches of each core. This guarantees that data is stored outside the cores and
minimizes latency by eliminating unnecessary core snoops to the Level 1 and Level 2 caches. Flags in
the Level 3 cache track which core’s cache supplied the original data. Therefore, if one core modifies
another core’s data in Level 3 cache, the Level 1 and Level 2 caches are updated as well. This
eliminates excessive inter-core traffic and ensures multi-level cache coherency.
Integrated memory controller
Instead of sharing a single pool of system memory, each processor accesses its own dedicated DDR3
system memory directly through an integrated memory controller. Three memory channels from each
memory controller to its dedicated memory provide a total bandwidth of 32 GB/s. The three memory
channels eliminate the bottleneck associated with earlier processor architectures in which all system
memory access took place through a single memory controller over the front side bus. When one
processor needs to access the memory of another processor, it can do so through the QuickPath
Interconnect.
QuickPath Interconnect controller
Xeon 5500 Series processors include the Intel QuickPath Architecture (Figure 2); high-speed, point-to-
point interconnects directly connect the processors. The Intel QuickPath Architecture also connects
each processor to distributed shared memory and to the I/O chipset. The interconnect performs a
maximum of 6.4 gigatransfers per second and has a bandwidth of 12.8 GB/s in each direction, for
a total bandwidth of 25.6 GB/s.
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