Technology and architecture of HP ProLiant AMD-based 100 - series G6 (Generation 6) servers

Figure 2. The H
yperTransport interconnect
HyperTransport can be configured through the Basic
Input/Output System (BIOS) and BIOS Setup
Utility (BSU). In the BSU Advanced Options menu, administrators can use the HyperTransport
Selection option to choose HT1 or HT3. HT1 is active by default.
HyperTransport is designed to provide a direct, scalable bandwidth interconnect between the
processor, the I/O subsystem, and the chipset. Due to chipset architecture in ProLiant AMD G6
servers, HT3 supports processor to processor communication, but not I/O operations.
HT Assist
HT Assist reduces cache coherence traffic on the HT links. By tracking where data is stored in cache
and guiding the processor directly to the data in the other processors’ caches, HT Assist reduces
cache probe traffic between processors, especially in 4- socket servers. Therefore, HT Assist results in
faster queries that can increase performance for cache-sensitive applications such as database,
virtualization, and compute-intensive applications.
Memory technologies
In the AMD Opteron 2400-series architecture, the memory controller is integrated into the processor
chip to optimize memory performance and bandwidth per CPU. The memory controller reduces
latency inherent in front side bus architectures by eliminating the bus contention between memory and
I/O cycles. AMD's memory bandwidth increases as processors are added to a configuration,
compared to legacy designs that scale poorly because access to main memory is limited by external
northbridge chips.
The AMD Opteron 2400-series processor supports dual memory channels. Two 64-bit-wide memory
channels operate in parallel to provide a 128-bit interface, so memory must be installed in pairs. The
AMD architecture uses:
4