HP ProLiant DL145 Generation 3 Server Software Configuration Guide

System BIOS configuration 28
Table 18 POST Beep Codes
Code Beep Description
14h Initialize keyboard controller
16h 1-2-2-3 BIOS ROM checksum
17h Initialize cache before memory auto size
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset programmable interrupt controller
20h 1-3-1-1 Test DRAM refresh
22h 1-3-1-3 Test 8742 keyboard controller
24h Set ES segment register to 4 GB
26h Enable gate A20 line
28h Autosize DRAM
29h Initialize POST memory manager
2Ah Clear 512 KB base RAM
2Bh Initialize extended CMOS
2Ch 1-3-4-1 RAM failure on address line xxxx
2Eh 1-3-4-3 RAM failure on data bits xxxx of low byte of memory bus
2Fh Enable cache before system BIOS shadow
30h RAM failure on data bits xxxx of high byte of memory bus
32h Test processor bus-clock frequency
33h Initialize Phoenix Dispatch Manager
34h Test CMOS
35h Reinitialize registers
36h Warm start shut down
37h Reinitialize chipset with initial POST values
38h Shadow system BIOS ROM
39h Reinitialize caches to initial POST values
3Ah Auto size cache
3Ch Advanced configuration of chipset registers
3Dh Load alternate registers with CMOS values
41h Initialize extended memory for ROM pilot
42h Initialize interrupt vectors
45h POST device initialization
46h 2-1-2-3 Check ROM copyright notice
48h Check video configuration against CMOS
49h Initialize PCI bus and devices
4Ah Initialize all video adapters in system
4Bh Quiet boot start (optional)
4Ch Shadow video BIOS ROM
4Eh Display BIOS copyright notice
4Fh Initialize multi-boot
50h Display processor type and speed