HP ProLiant DL145 Generation 3 Server Software Configuration Guide

System BIOS configuration 27
POST beep codes
There are several POST routines that issue a POST terminal error and shut down the system if they fail. Before
shutting down the system, the terminal-error handler issues a beep code signifying the test point error, writes the
error to port 80h, attempts to initialize the video, and writes the error in the upper left corner of the screen (using
both mono and color adapters).
NOTE: An optional POST code expansion board must be installed in the server for the POST beep codes to be
audible.
The POST routines cannot display messages when an error occurs if any of the following are present:
• The error occurs before the video display is initialized.
• The video configuration fails, either there’s no graphics card installed or the one installed is faulty.
• An external ROM module does not properly checksum to zero.
• The system memory cannot be initialized.
If an optional POST code expansion board is installed in the server, during these instances, the server emits a
buzzing sound followed by a series of audible beeps. An external ROM module can also issue audible errors,
usually consisting of one long tone followed by a series of short tones. If you get a blank screen on boot but hear
beeps, count the beeps and refer to Table 18 for their corresponding meaning. If you miss the beep code:
1. Turn off the server by pressing the power button for five seconds or more.
2. Restart the server by pressing the power button.
3. Listen for the signal again.
The routine derives the beep code from the test point error as follows:
1. The 8-bit error code is broken down to four 2-bit groups (Discard the most significant group if it is 00).
2. Each group is made one-based (1 through 4) by adding 1.
3. Short beeps are generated for the number in each group.
Example:
Test point 01Ah = 00 01 10 10 = 1-2-3-3 beeps
Table 18 lists the checkpoint codes written at the start of each test and the beep codes issued for terminal errors.
Table 18 POST Beep Codes
Code Beep Description
01h Initialize IPMI
02h Verify real mode
03h Disable non-maskable interrupts
04h Get processor type
06h Initialize system hardware
07h Disable shadow and execute code from the ROM
08h Initialize chipset with initial POST values
09h Set IN POST flag
0Ah Initialize processor registers
0Bh Enable processor cache
0Ch Initialize caches to initial POST values
0Eh Initialize I/O component
0Fh Initialize the local bus IDE
10h Initialize power management
11h Load alternate registers with initial POST values
12h Restore processor control word during warm boot
13h Initialize PCI bus mastering devices