Technologies in HP ProLiant G7 c-Class server blades with AMD Opteron™ processors, 3rd Edition

• Two dual-rank DIMMs per channel result in four--way bank interleaving.

• Two quad-rank DIMMs per channel result in eight-way bank interleaving.

• Two dual-rank DIMMs and one quad-rank DIMM result in eight-way bank interleaving, in servers using three

DIMMs per channel.

Memory channel interleaving

Memory channel interleaving transfers data by alternate routing through the two available memory channels. As a

result, when the memory controller must access a block of logically contiguous memory, the requests don’t stack up

in the queue of a single channel. Alternate routing decreases memory access latency and increases performance.

However, memory channel interleaving increases the probability that more DIMMs must remain in an active state.

Memory channel interleaving is always active on AMD Opteron 6200 Series processors.

Memory node interleaving

Node interleaving can interleave memory across any subset of nodes in the multi-processor system. Node

interleaving breaks memory into 4 KB addressable entities and assigns blocks of addresses to the nodes in the

sequence indicated in Table 2.

Table 2: Sequencing of memory node interleaving across multiprocessor systems

Node Assigned Addresses

0 0 – 4095

1 4096 – 8191

2 8192 – 12287

3 12888 – 16383

Address 16384 is assigned to node 0, and the process continues to assign all memory in this fashion. An

application that uses a common allocation thread will benefit from node interleaving.

The default configuration disables memory node interleaving. You can activate node interleaving using the RBSU.

You can only configure memory node interleaving if the memory footprint for all processors is identical.

Error correction

In AMD Opteron 6200 Series processors, the memory controller supports ECC for both x4 and x8 DIMMs.

In 1996, we introduced Advanced Memory Protection (AMP). It used enhanced ECC algorithms to detect and

correct up to four bad bits of data. The HP intelligent correctible memory error threshold algorithm is a development

outgrowth of AMP. The algorithm analyzes the probability of system failure when two independently correctable

errors on the same rank combine to form an uncorrectable error.

The HP intelligent correctable memory error threshold algorithm replaced existing AMP protection in mid-2011 for

AMD G7 servers.

I/O technologies

HP ProLiant c-Class Server Blades support PCI Express (PCIe), serial attached SCSI (SAS), and serial ATA (SATA)

I/O technologies. They support multi-function 1 Gb or 10 Gb Ethernet, 4 Gb Fibre Channel, and 4X DDR (20 Gb)

or QDR InfiniBand.