HP 9000 rp8420 Server - User Service Guide, Fifth Edition

Main Memory Performance
Latency to main memory is an important parameter in determining overall system performance.
For a server with memory busses at 125MHz, the latency for a page hit is 8.5 cycles (68ns), the
latency for a page closed is 11.5 cycles (92ns), and the latency for a page miss is 14.5 cycles (116ns).
Valid Memory Configurations
The HP 9000 rp8420 server is capable of supporting as little as 0.5GB of main memory using two
256MB DIMMs installed on one of the cell boards and as much as 256 GB by filling all 16 DIMM
slots on all four cell boards with 4GB DIMMs.
DIMMs must be loaded in sets of two at specified locations on the cell board. Two DIMMs are
called an “echelon,” so two echelons would be equivalent to four DIMMs, three echelons would
be equivalent to six DIMMs, and so on. The DIMMs must be the same size in an echelon. The
DIMMs across all cells in a partition should have identical memory loaded. Figure 1-8 shows the
DIMM slot layout on the cell board. See Table 1-3 and Figure 1-8 for DIMM load order and layout
on the cell board.
A quad, as seen in Figure 1-8, is a grouping of four DIMMs. Configurations with 8 or 16 DIMM
slots loaded are recommended. The DIMM sizes in a quad can be different, but the DIMMs in
an echelon must be the same size.
Table 1-3 DIMM Load Order
Quad LocationDIMM Location on Cell
Board
Action TakenNumber of DIMMs Installed
Quad 00A and 0BInstall First2 DIMMs = 1 Echelon
Quad 11A and 1BAdd Second4 DIMMs = 2 Echelons
Quad 22A and 2BAdd Third6 DIMMs = 3 Echelons
Quad 33A and 3BAdd Fourth8 DIMMs = 4 Echelons
Quad 04A and 4BAdd Fifth10 DIMMs = 5 Echelons
Quad 15A and 5BAdd Sixth12 DIMMs = 6 Echelons
Quad 26A and 6BAdd Seventh14 DIMMs = 7 Echelons
Quad 37A and 7BAdd Last16 DIMMs = 8 Echelons
Detailed HP 9000 rp8420 server Description 27