DDR3 memory technology

Introduction

DDR3, the third generation of Dual Data Rate (DDR) Synchronous DRAM memory, delivers significant

performance and capacity improvements over older DDR2 memory. HP introduced DDR3 memory

with the G6 and G7 ProLiant servers, coinciding with the transition to server architectures that use

distributed memory and on-processor memory controllers. DDR3 continues to evolve in terms of speed

and memory channel capacity, and the new HP ProLiant Gen8 servers fully support these

improvements. This paper provides a detailed look at the core technologies that enable DDR3

memory and its benefits as well as the integration of DDR3 with the current server architectures.

Beginning with ProLiant Gen8 servers, we are introducing HP SmartMemory technology for DDR3

memory. HP SmartMemory DIMMs have passed our qualification and testing processes. Gen8 servers

configured with HP SmartMemory DIMMs deliver extended performance and manageability that is

not supported using third party DIMMs.

DDR3 architecture

DDR3 uses the same basic DRAM configuration and architecture as previous DDR implementations.

Each DIMM consists of ranks of 9 or 18 DRAMs that deliver 72 bits—64 bits of data and 8 bits of

ECC (error correction code)—in parallel to the memory bus to the CPU. DDR3 natively supports

addressing up to eight banks, or ranks, of memory on a given memory channel. An individual DIMM

module may support one, two, or four banks of these DRAMs, creating single-, dual-, or quad- ranked

DIMM modules. The capacity of the DRAMs used and the number of ranks determine the overall

capacity of a DIMM. DDR3 defines up to an 8 Gigabit DRAM, which will eventually lead to an

individual DDR3 quad-rank DIMMs with a capacity as large as 64 GB.

Types of DDR3 DIMMs

DDR3 initially supported two types of DIMM memory—Unbuffered DIMMs (UDIMMs) and Registered

DIMMs (RDIMMs). ProLiant Gen8 servers will support new third type memory we call Load Reduced

DIMM, or LRDIMM.

Unbuffered and Registered DIMMs

With Unbuffered DIMMs (UDIMMs), all address and control signals, as well as the data lines, connect

directly to the memory controller across the DIMM connector. Without buffering, each additional

UDIMM that you install on a memory channel increases the electrical load. As a result, UDIMMs are

limited to a maximum of two dual-rank UDIMMs per memory channel. In smaller memory

configurations, UDIMMs offer the fastest memory speeds with the lowest latencies.

Registered DIMMs (RDIMM) lessen direct electrical loading by having a register on the DIMM to

buffer the Address and Command signals between the DRAMs and the memory controller. The

overall load on the address portion of the memory channel. The data from an RDIMM still flows in

parallel as 72 bits (64 data and 8 ECC) across the data portion of the memory bus. With RDIMMs,

each memory channel can support up to three dual-rank DDR3 RDIMMs or two quad-rank RDIMMs.

With RDIMMs, the partial buffering slightly increases power consumption and latencies.

Fully Buffered DIMMs (FBDIMMs), which buffer all memory signals (address, control, and data)

through an Advanced Memory Buffer (AMB) chip on each DIMM, are not part of DDR3. FBDIMM

architecture supported more DIMMs on each memory channel, but FBDIMMs were more costly, used

more power, and had increased latency. The greater number of memory channels in server