Service manual

System Overview 1-21
Chip Description
Unit Description
Instruction 8-byte cache, 4-way issue
Execution 4-way execution; 2 integer units, 1 floating-point adder,
1 floating-point multiplier
Memory Merge logic, 8-Kbyte write-through first-level data cache,
96-Kbyte write-back second-level data cache, bus
interface unit
CPU Variants
Module Variant Clock Frequency Onboard Cache
B3001-CA 300 MHz None
B3002-AB 300 MHz 2 Mbytes
B3004-BA 300 MHz 2 Mbytes
B3004-AA 400 MHz 4 Mbytes
B3004-DA 466 MHz 4 Mbytes
CPU Configuration Rules
• The first CPU must be in CPU slot 0 to provide the system clock.
• Additional CPU modules should be installed in ascending order by slot number.
• All CPUs must have the same Alpha chip clock speed. The system bus will
hang without an error message if the oscillators clocking the CPUs are different.
• Mixing of cached and uncached CPUs is not supported.
Color Codes
The top edge of the CPU module variant is color coded for easy identification.
Color
Option
Number Description
Dark Blue B3001-CA 300 MHz, uncached
Green B3002-AB 300 MHz, 2MB cached
Green B3004-BA 300 MHz, 2MB cached
Orange B3004-AA 400 MHz, 4MB cached
Red B3004-DA 466 MHz, 4MB cached